Digital Design · ASIC Synthesis
Multiplier-Free Spiking Neuron (LIF) in 22nm
A Leaky Integrate-and-Fire neuron in SystemVerilog that replaces multiply-based leakage decay with arithmetic bit-shifts. It synthesizes to zero multipliers and ~96.7 µm² on an Intel 22nm FinFET PDK.
- DSP / multiplier blocks
- 0
- cell area
- ~96.7 µm²
- sequential registers
- 17
- combinational cells
- 162
The problem
Spiking neural networks are attractive for low-power inference. But a naive Leaky Integrate-and-Fire (LIF) neuron multiplies its membrane potential by a decay factor every timestep, and multipliers are expensive in area and power. When thousands of neurons are replicated, that cost dominates.
Approach
- Shift-based leakage. I designed the RTL so leakage decay is an arithmetic right bit-shift rather than a multiplication. This removes the need for DSP and multiplier hardware entirely.
- Model-to-RTL check. I used a PyTorch reference model to compare neuron behavior against the hardware implementation.
- Simulation and synthesis. I verified the RTL in Cadence Xcelium. I then ran automated gate-level ASIC synthesis with Cadence Genus on an Intel 22nm FinFET PDK.
Results
| Metric | Result |
|---|---|
| DSP / multiplier blocks | 0 |
| Sequential registers | 17 |
| Combinational cells | 162 |
| Cell area | ~96.7 µm² |