Luke Neilson

Hardware · Analog/Mixed-Signal · Digital Logic

Luke Neilson

Honors Electrical & Computer Engineering student at Oregon State University, building hardware for energy-efficient and neuromorphic computing, from device-level simulation and ADC specs to RTL and transistor-level design.

Former NCAA Division I rower. I bring the same discipline, work capacity and composure under pressure to every engineering problem.

  • GPA 3.91
  • Degree H.B.S. ECE, Minor CS
  • Grad June 2027
Resume LinkedIn
Portrait of Luke Neilson

Featured work

Projects

Selected work across mixed-signal circuits, digital ASIC design and embedded instrumentation.

Honors Thesis · Brain-Inspired Computing Lab

In progress

Reservoir Computing Hardware on ESO Memristors

Readout and driver circuitry for a reservoir computer built on entropy-stabilized oxide (ESO) memristors, targeting TSMC 65nm. Hardware limits are modeled in simulation before any silicon is committed.

ADC spec set by sweeps
3-bit
Audio-MNIST accuracy
~98.5%
real devices validated against
16
TSMC target node
65nm
  • PyTorch
  • Slurm / H100 HPC
  • Cadence Virtuoso
  • Mixed-Signal
  • ADC / DAC
  • TSMC 65nm

Digital Design · ASIC Synthesis

Multiplier-Free Spiking Neuron (LIF) in 16nm

A Leaky Integrate-and-Fire neuron in SystemVerilog that replaces multiply-based leakage decay with arithmetic bit-shifts. It synthesizes to zero multipliers and ~96.7 µm² on an Intel 16nm FinFET PDK.

DSP / multiplier blocks
0
cell area
~96.7 µm²
sequential registers
17
combinational cells
162
  • SystemVerilog
  • PyTorch
  • Cadence Xcelium
  • Synopsys Design Compiler
  • Intel 16nm FinFET

Junior Design (ECE 342) · PCB & Mixed-Signal

Dual-Channel 34 MSa/s USB Oscilloscope

A USB-powered, two-channel oscilloscope built by a team of three. I led the schematic and the 4-layer PCB layout across both revisions and designed the microcontroller block. It samples at 34 MSa/s per channel, more than 11× the previous course record of 3 MSa/s.

per channel
34 MSa/s
previous course record (3 MSa/s)
11×
PCB, BGA microcontroller
4-layer
rev-1 to rev-2 re-spin
5 days
  • NXP LPC4370
  • KiCad
  • 4-Layer PCB
  • Analog Front End
  • Op-Amps
  • JLCPCB / LCSC
Source

Also

Research, industry & athletics

Experience & Leadership

  1. Spring 2026 – Present

    Undergraduate Researcher, Honors Thesis

    Brain-Inspired Computing Lab, Oregon State University

    • Hardware for reservoir computing on entropy-stabilized oxide memristors, targeting TSMC 65nm.
    • Hardware-aware PyTorch simulation (TIA readout, ADC quantization, ENOB noise) on an H100 cluster via Slurm; set a 3-bit ADC spec at ~98.5% Audio-MNIST accuracy.
    • Fixed readout-training bugs in group code and validated simulations against measured data from 16 devices; now designing the DAC input driver in Cadence Virtuoso.
    Project details
  2. Summer 2026

    Electrical Engineering Intern, Wind Energy

    Mortenson

    • Independently managed a complex decommissioning scope for six weeks on a wind energy project.
    • Coordinated multiple subcontractors while balancing safety and production through 72+ hour weeks.
    • Created QA/QC standardization checklists.
  3. 2024 – 2025

    NCAA Division I Rower

    Oregon State University Men's Rowing

    • Walked on with no rowing experience, reached the top tier of the roster and competed at the IRA National Championships.
    • Trained 20+ hours a week while holding a 3.91 GPA, then concluded athletics to focus fully on engineering.
  4. 2024

    Undergraduate Researcher, Microscale Design (URSA)

    Oregon State University

    • Designed piezoelectric S-drive MEMS accelerometer variations in AutoCAD (Jason Clark, PhD).
    • Wrote a published article on the ethical and economic impacts of sensor automation.

Proposal

NSF GRFP Applicant, Fall 2026

Proposed a physics-informed, AI-driven EDA framework that builds analog non-idealities (IR drop, sneak paths, device noise) directly into layout optimization for energy-efficient and neuromorphic hardware.

Honors

Academic Recognition

  • Tau Beta Pi Engineering Honor Society
  • Drucilla Shepard Smith Award (4.0 GPA)
  • Oregon State University Honors College

Self-financed my education working 60+ hour weeks in high-volume hospitality alongside school.

Toolbox

Skills

Hardware & Architecture

  • Mixed-Signal Circuit Design
  • MIPS Architecture
  • Microcontrollers (ATmega32U4, NXP LPC4370)
  • FPGA (DE-10 Lite)
  • Circuit Analysis
  • Oscilloscopes & Lab Instruments

Languages

  • SystemVerilog
  • Verilog
  • C
  • C++
  • AVR Assembly
  • Bash / Shell
  • TCL

EDA & Process

  • Cadence Virtuoso
  • Cadence Xcelium
  • Synopsys Design Compiler
  • LTspice
  • ModelSim
  • GTKWave
  • Quartus
  • Vivado
  • KiCad
  • AutoCAD
  • TSMC 65nm
  • Intel 16nm & 22FFL

Compute & ML

  • PyTorch
  • Slurm / HPC
  • Unix Process API

Contact

Let's talk hardware.

I'm interested in roles in analog/mixed-signal design, digital design and verification, embedded systems and hardware for AI/ML. The fastest way to reach me is email.

Based in Oregon

LinkedIn Resume (PDF)